This invention relates to system resource controllers and particularly to bus masters accessing system resources via a bus.
Large data processing systems include many resources and many demands on the resources. The number and diversity of the resources and the devices that access the resources are so great that the system processor cannot efficiently control the interaction among all the resources and devices. Direct memory access was developed to permit memory accesses by devices without requiring processor intervention. DMA controllers are commercially available and are programmable so that their operation can be tailored to a particular system.
When several devices contend for access to the system resources, usually the buses connecting devices and resources, the access is granted one of the contenders on the basis of arbitration. Devices are assigned priorities so that the faster devices can transfer the data that accumulates at a high rate.
When one device attains control of the resource, it may make several data transfers. When finished, it relinquishes control of the resource. Then arbitration for access by another device can be initiated.
The time for making data transfers is now measured in nanoseconds so the systems can operate at fast rates. Even at high speeds, it is desirable to make the system operation as efficient as possible.
When a device releases a resource, the arbitration for the next access takes a cycle during which the resource is idle.
Sometimes a device will hang up because of a malfunction such as addressing a nonexistent location or resource which results in a lack of response so that the device does not continue its operation.
Another problem that arises in large, complicated systems is that after a system has been constructed, it does not operate as designed. Errors occur and the system is halted.
These problems are solved by the present invention by determining when one or two more transfers remain in an access by a device and supplies signals that permit the arbitration to be made during the last transfer so that the next device access can commence in the cycle following the last transfer by the preceding device.
The device is reset by a timer that measures the elapsed time between steps in the sequence of transferring data. Too much time between steps indicates that the device is hung up.
By selectively masking the errors from stopping the device, the system problems can be analyzed and corrected.
A device is usually controlled by a bus master that assumes control of a bus when access is granted and supplies the signals necessary to make the data transfers. In the broadest sense, the bus master is a system resource master because access to resources other than buses may be required.
Page printers are so named because they operate by composing an entire page before printing as contrasted to line printers which print a line at a time. The advantage of page printers is that graphics, images, and data can be easily composed on a single page very quickly. Page printers are usually laser types and print one hundred or more pages per minute. Page printers can also print text and images in varying orientations, i.e., in any of the four 90-degree rotations on the page to support landscape and portrait orientations as well as duplex and tumble duplex.
Storing all the text font and image data for each of the four possible orientations would require an inordinate amount of memory so logic circuits used to rotate fonts and images to the desired orientation during data transfer using the image data arranged in quads, i.e., four-by-four arrays of pels, each pel being represented by a bit.
To compose an entire page requires a large amount of memory. At 240 pels per inch resolution, an 81/2-by-11 inch (A-size) page contains 5,385,600 pels. To compose one page while another is printing would require twice as much memory, viz., 10,771,200 bits at one bit per pel. To reduce memory requirements, printer control units are designed with only enough raster buffer memory to contain a small width or swath of pels to be printed on each page. As a page is printed, the swath is filled with pels for each successive portion of the page.
The swath is composed in a raster buffer, so named because the laser printhead causes the page to be printed in raster fashion. Whenever an image is larger than the swath width, the image must be subdivided into rectangular tiles that will fit in the swath buffer. (This subdivision is called tessellation.)
In accordance with the invention, a system resource master, which can be a bus master, for transferring data via a system resource such as a bus, the access to the bus being arbitrated on the basis of request signals from a plurality of bus masters, includes supplying signals to continue access to the bus by holding off arbitration of access to the bus by other bus masters. Determination that a given number of transfers remain inhibits the supplied signals so that arbitration for access to the bus can be initiated while the remaining transfers are made.
The bus master sequencer for controlling the steps involved in communicating with the bus has a timeout device for timing delays between steps controlled by the sequencer. The timeout device resets the sequencer when a predetermined time has elapsed between consecutive steps.
The sequencer is responsive to error signals for inhibiting the sequencer when an error occurs but the errors can be selectively prevented from inhibiting the sequencer.